Simple test

Ensure your device works with this simple test.

examples/si5351_simpletest.py
 1# SPDX-FileCopyrightText: 2021 ladyada for Adafruit Industries
 2# SPDX-License-Identifier: MIT
 3
 4# Simple demo of the SI5351 clock generator.
 5# This is like the Arduino library example:
 6#   https://github.com/adafruit/Adafruit_Si5351_Library/blob/master/examples/si5351/si5351.ino
 7# Which will configure the chip with:
 8#  - PLL A at 900mhz
 9#  - PLL B at 616.66667mhz
10#  - Clock 0 at 112.5mhz, using PLL A as a source divided by 8
11#  - Clock 1 at 13.553115mhz, using PLL B as a source divided by 45.5
12#  - Clock 2 at 10.76khz, using PLL B as a source divided by 900 and further
13#    divided with an R divider of 64.
14import board
15import busio
16
17import adafruit_si5351
18
19# Initialize I2C bus.
20i2c = busio.I2C(board.SCL, board.SDA)
21
22# Initialize SI5351.
23si5351 = adafruit_si5351.SI5351(i2c)
24# Alternatively you can specify the I2C address if it has been changed:
25# si5351 = adafruit_si5351.SI5351(i2c, address=0x61)
26
27# Now configue the PLLs and clock outputs.
28# The PLLs can be configured with a multiplier and division of the on-board
29# 25mhz reference crystal.  For example configure PLL A to 900mhz by multiplying
30# by 36.  This uses an integer multiplier which is more accurate over time
31# but allows less of a range of frequencies compared to a fractional
32# multiplier shown next.
33si5351.pll_a.configure_integer(36)  # Multiply 25mhz by 36
34print(f"PLL A frequency: {si5351.pll_a.frequency / 1000000}mhz")
35
36# And next configure PLL B to 616.6667mhz by multiplying 25mhz by 24.667 using
37# the fractional multiplier configuration.  Notice you specify the integer
38# multiplier and then a numerator and denominator as separate values, i.e.
39# numerator 2 and denominator 3 means 2/3 or 0.667.  This fractional
40# configuration is susceptible to some jitter over time but can set a larger
41# range of frequencies.
42si5351.pll_b.configure_fractional(24, 2, 3)  # Multiply 25mhz by 24.667 (24 2/3)
43print(f"PLL B frequency: {si5351.pll_b.frequency / 1000000}mhz")
44
45# Now configure the clock outputs.  Each is driven by a PLL frequency as input
46# and then further divides that down to a specific frequency.
47# Configure clock 0 output to be driven by PLL A divided by 8, so an output
48# of 112.5mhz (900mhz / 8).  Again this uses the most precise integer division
49# but can't set as wide a range of values.
50si5351.clock_0.configure_integer(si5351.pll_a, 8)
51print(f"Clock 0: {si5351.clock_0.frequency / 1000000}mhz")
52
53# Next configure clock 1 to be driven by PLL B divided by 45.5 to get
54# 13.5531mhz (616.6667mhz / 45.5).  This uses fractional division and again
55# notice the numerator and denominator are explicitly specified.  This is less
56# precise but allows a large range of frequencies.
57si5351.clock_1.configure_fractional(si5351.pll_b, 45, 1, 2)  # Divide by 45.5 (45 1/2)
58print(f"Clock 1: {si5351.clock_1.frequency / 1000000}mhz")
59
60# Finally configure clock 2 to be driven by PLL B divided once by 900 to get
61# down to 685.15 khz and then further divided by a special R divider that
62# divides 685.15 khz by 64 to get a final output of 10.706khz.
63si5351.clock_2.configure_integer(si5351.pll_b, 900)
64# Set the R divider, this can be a value of:
65#  - R_DIV_1: divider of 1
66#  - R_DIV_2: divider of 2
67#  - R_DIV_4: divider of 4
68#  - R_DIV_8: divider of 8
69#  - R_DIV_16: divider of 16
70#  - R_DIV_32: divider of 32
71#  - R_DIV_64: divider of 64
72#  - R_DIV_128: divider of 128
73si5351.clock_2.r_divider = adafruit_si5351.R_DIV_64
74print(f"Clock 2: {si5351.clock_2.frequency / 1000}khz")
75
76# After configuring PLLs and clocks, enable the outputs.
77si5351.outputs_enabled = True
78# You can disable them by setting false.